In a nanoscale regime, the performance of field effect transistors (FETs) is challenged by current leakage through a body of the semiconductor as well as transport through an inversion layer defined by single-sided (top) gate electrode, for example as found with a planar transistor. This leakage is usually ignored in macro/micro-scale devices since these devices are properly understood with one-dimensional physics. Traditional FET designs apply the gate from the top surface of the transistor device. As device dimensions continue to shrink to about 10 nm, a single sided transistor gate does not provide sufficient control, as evidenced by increases in sub-threshold current and more gradual transition as the device is switched.
Recent advances in transistor technology include a tri-gate transistor which has gate portions around three sides of the channel. This structure is similar to a FinFET design, for example as discussed in “A comprehensive review on microwave FinFET modeling for progressing beyond the state of art,” G. Crupi, D. M. M.-P. Schreurs, J.-P. Raskin and A. Caddemi, Solid-State Electron. 80, 81-95 (2013). In all nanowire FET geometries, it is necessary to provide low resistance contacts between the source, the nanowire conductance region, and the drain, and to provide a high-resistance insulating layer (e.g., gate oxide) between the gate electrode and the conducting nanowire channel. In Si-based FETs, SiO2 is most often used for this layer, although there has been intensive research in higher dielectric constant materials as device scaling has progressed into the nanoscale regime. In FETs using a Group III-V semiconductor as a bulk material, an insulating gate oxide is necessary to enhance device performance and lifetime by suppressing gate current. An alternative is to use a higher bandgap III-V alloy in a metal-semiconductor FET (MESFET) geometry, but the lower bandgap difference between the III-V alloys comprising the conducting and isolating layer restrict device performance. GaN-based devices are often configured as high electron mobility transistors (HEMTs) due to the large intrinsic channel conductance, which is caused by the spontaneous formation of a two-dimensional electron gas (2DEG) at the AlGaN/GaN interface. Such devices typically utilize SiO2 or SiNx as a gate insulator, but the high resistivity of GaN-based materials also permits the use of semi-insulating AlGaN layers to isolate the gate from the channel.
Much of the recent discussion of nanowire transistors has been focused on a vertical geometry where the nanowires are grown perpendicular to the substrate semiconductor material. For a recent review see, J. K. Hyun, S. Zhang and L. J. Lauhon, Nanowire Heterostructures, Ann. Rev. Mat'l Res. 43, 451-479 (2013). This results in several difficult fabrication issues in using these nanowires in complex circuits. In particular, low resistance, ohmic contact has to be made to the very small cross section at the as-grown tip of the vertical nanowires, a difficult metallurgical problem. Second, vertical nanowires are often grown by a vapor-liquid-solid process using metal seeds that results in somewhat random positioning and significant variations in wire diameters, as well as the potential for deep level impurity incorporation into the nanowires. Third, it is difficult to envision nanowire size selection and placement technologies for the manufacture of interconnected circuit geometries involving many transistors in series/parallel combinations as is customary in today's integrated circuits.
In contrast, all of the device geometries disclosed herein provide for nanowires parallel to, but isolated from, the substrate surface. Contacts are based on single crystal semiconductor interfaces to larger area bulk semiconductors where the contact metallurgy is well developed. The wire geometries are defined by lithographic processes allowing for controlled and uniform nanowire dimensions, complex and flexible interconnection geometries. Materials are grown by homogeneous and heterogeneous epitaxial processes or etched by well developed processes known to produce only low concentrations of defects and without the need for metal seeds. Also, these lithographically defined geometries provide versatility in designating the length and lateral dimensions of the gates, directly related to the level of drain current and transconductance for various applications, and circuit layout interconnections.